UNIT II Computer System Architecture

Q1) Which type of addressing mode, less number of memory references are required?

Solution:

Implied

In this type we don’t need any memory reference. As it specify its instruction itself.

Example: CLC (Used to reset carry flag to 0)

Q2) How many bit strings of length ten either start with a 1 bit or end with two bits 00?

Solution

Case 1: 1 – – – – – – – – –

Case 2: – – – – – – – – 0 0

Case 3: 1 – – – – – – – 0 0

Total length = 10

Case 1: Start with 1, remaining 9 dash is vacant. So i cant do anything

So possible case 2⁹

2 used therefore vacant 9 places can hold 2 types of value ie (0,1)

Case 2 Total = 10, 2 used

So, 28 Possible cases

Case 3: Total 10, 3 used

So, 27 possible cases

So, 29 + 28 - 27  = 512 + 256 - 128
                 = 768 - 128
                 = 640

Q3) The fault can be easily diagnosed in micro-prog control unit using diagnostic tools by maintaining te contents of

Solution: Flags, Registers & Counters (are essential in microprogram)

Q4) How many address lines & data lines are requires to provide a memory capacity of 16k*16?

Solution: Memory Size = 16k where k means 1000 But in digital electronics 1000 would have been 1024

= 16 * k

= 16 * 1024

= 2⁴ * 2¹⁰

Number of address line = 4 + 10 = 14

So Answer is 14, 16

ROM Size = 2^m * n => For future use only

Q5) How many 3k * 1 RAM chips are needed to provide a memory capacity of 256k-Bytes?

Solution

256 kbytes ie 256 * 1024 * 8 bits

RAM Chips capacity 32 kbits = 32*1024 bits

= (256 * 1024 * 8)/(32*1024)

= 64

Q6) A processor can support maximum memory of 4GB where memory is word addressable and a word is 2 bytes. what will be the size of address bus of the processor?

Solution

Maximum memory = 4 GB (2³² Bytes)

Word Size = 2 bytes

Size of Memory (Address Bus) = Number of word Addressable / Number of bits per word

= 2³² / 2

= 2³² * 2^-1

= 2³¹

= 31 bits

Q7) Matches

• 2421 – Self Complementing
• Control Memory – Microprogrammed Control Unit
• Register – Storage Unit
• Associative Mapping – Cache Memory

Q8) Matches

• Micro Operation – Elementary Operation Performed on data stored in registers
• Interrupts – Improve CPU Utilization
• Micro Instructions – Specify micro operations

Q9) Instruction stored at location 500 with address field at 501. Address field has 400 value. Processor Register R1 contains 200 No. Match address mode with its effective address

Solution:

1. Direct Address – 400
2. Relative Address – Next memory location + Direct Address Value (500 + 400 = 900)
3. Register Indirect Address(RIA) – 200
4. Indexed Address – RIA + Direct Address (200 + 400 = 600)

Q10) A non pipelined system takes 30ns to process a task. Same task can be processed in 4 segment pipeline with clock cycle of 10 ns. Determine Speed up of pipeline for 100 tasks.

Solution

Speed up Ratio (S) = nt_n / (k + n-1) t_p

Where n = number of tasks = 100

t_n = time taken = 30ns

k = number of segments = 4

t_p = time for one clock cycle = 10ns

Therefore, 100 * 30 / (4+100-1) 10

= 3000 / 1030

= 2.91